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ATmega128
The EEPROM can not be programmed during a CPU write to the Flash memory. The software
must check that the Flash programming is completed before initiating a new EEPROM write.
Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the
Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader
Support – Read- W hile- W rite Self-Programming ” on page 273 for details about boot
programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master W rite Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the
interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared
during the four last steps to avoid these problems.
W hen the write access time has elapsed, the EE W E bit is cleared by hardware. The user soft-
ware can poll this bit and wait for a zero before writing the next byte. W hen EE W E has been set,
the CPU is halted for two cycles before the next instruction is executed.
? Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. W hen the correct
address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. W hen the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed.
The user should poll the EE W E bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated Oscillator is used to time the EEPROM accesses. Table 2 lists the typical pro-
gramming time for EEPROM access from the CPU.
Table 2. EEPROM Programming Time
Number of Calibrated RC
Symbol
EEPROM W rite (from CPU)
Oscillator Cycles (1)
8448
Typ Programming Time
8.5ms
Note:
1. Uses 1MHz clock, independent of CKSEL-fuse settings.
22
2467X–AVR–06/11
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